| AFGA |
OPERATING TEMP RANGE |
-55.0/+125.0 DEG CELSIUS |
| CQZP |
INPUT CIRCUIT PATTERN |
9 INPUT |
| CSSL |
DESIGN FUNCTION AND QUANTITY |
1 FLIP-FLOP, J-K, AND INPUT MASTER SLAVE AND 1 FLIP-FLOP, J-K, CLOCKED |
| CZEN |
VOLTAGE RATING AND TYPE PER CHARACTERISTIC |
-1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |
| CQSZ |
INCLOSURE CONFIGURATION |
FLAT PACK |
| TTQY |
TERMINAL TYPE AND QUANTITY |
14 FLAT LEADS |
| AFJQ |
STORAGE TEMP RANGE |
-65.0/+150.0 DEG CELSIUS |
| ADAT |
BODY WIDTH |
0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM |
| CBBL |
FEATURES PROVIDED |
HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND MEDIUM POWER AND EDGE TRIGGERED AND PRESETTABLE AND MEDIUM SPEED AND W/CLEAR |
| ADAU |
BODY HEIGHT |
0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM |
| CQSJ |
INCLOSURE MATERIAL |
CERAMIC AND GLASS |
| CQWX |
OUTPUT LOGIC FORM |
TRANSISTOR-TRANSISTOR LOGIC |
| ADAQ |
BODY LENGTH |
0.337 INCHES MINIMUM AND 0.350 INCHES MAXIMUM |
| CZEQ |
TIME RATING PER CHACTERISTIC |
39.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CTFT |
CASE OUTLINE SOURCE AND DESIGNATOR |
-0-004-AA JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| TEST |
TEST DATA DOCUMENT |
80249-911252 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| AEHX |
MAXIMUM POWER DISSIPATION RATING |
110.0 MILLIWATTS |
| CWSG |
TERMINAL SURFACE TREATMENT |
SOLDER |