| CBBL |
FEATURES PROVIDED |
EDGE TRIGGERED AND W/ENABLE AND ASYNCHRONOUS AND POSITIVE OUTPUTS AND MEDIUM POWER AND MEDIUM SPEED AND HERMETICALLY SEALED AND MONOLITHIC AND W/CLEAR |
| AFGA |
OPERATING TEMP RANGE |
-55.0/+125.0 DEG CELSIUS |
| CQWX |
OUTPUT LOGIC FORM |
DIODE-TRANSISTOR LOGIC |
| PRMT |
PRECIOUS MATERIAL |
GOLD |
| ADAT |
BODY WIDTH |
0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| CTFT |
CASE OUTLINE SOURCE AND DESIGNATOR |
T0-86 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| CQSZ |
INCLOSURE CONFIGURATION |
FLAT PACK |
| PMLC |
PRECIOUS MATERIAL AND LOCATION |
TERMINALS GOLD |
| AFJQ |
STORAGE TEMP RANGE |
-65.0/+150.0 DEG CELSIUS |
| ADAU |
BODY HEIGHT |
0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| CQSJ |
INCLOSURE MATERIAL |
CERAMIC AND GLASS |
| ADAQ |
BODY LENGTH |
0.240 INCHES MINIMUM AND 0.275 INCHES MAXIMUM |
| CQZP |
INPUT CIRCUIT PATTERN |
8 INPUT |
| AEHX |
MAXIMUM POWER DISSIPATION RATING |
70.0 MILLIWATTS |
| CZEQ |
TIME RATING PER CHACTERISTIC |
35.00 NANOSECONDS MINIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 75.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 30.00 NANOSECONDS MINIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT AND 75.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CSSL |
DESIGN FUNCTION AND QUANTITY |
2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |