| CQSZ |
INCLOSURE CONFIGURATION |
DUAL-IN-LINE |
| AFGA |
OPERATING TEMP RANGE |
-55.0/+125.0 DEG CELSIUS |
| CSSL |
DESIGN FUNCTION AND QUANTITY |
4 BUFFER AND 4 GATE, NAND |
| ADAQ |
BODY LENGTH |
0.755 INCHES MINIMUM AND 0.786 INCHES MAXIMUM |
| TTQY |
TERMINAL TYPE AND QUANTITY |
14 PRINTED CIRCUIT |
| AEHX |
MAXIMUM POWER DISSIPATION RATING |
500.0 MILLIWATTS |
| ADAU |
BODY HEIGHT |
0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| AFJQ |
STORAGE TEMP RANGE |
-65.0/+150.0 DEG CELSIUS |
| TEST |
TEST DATA DOCUMENT |
99971-7540587 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| CZEN |
VOLTAGE RATING AND TYPE PER CHARACTERISTIC |
5.5 VOLTS MAXIMUM POWER SOURCE |
| CQSJ |
INCLOSURE MATERIAL |
CERAMIC AND GLASS |
| CQWX |
OUTPUT LOGIC FORM |
TRANSISTOR-TRANSISTOR LOGIC |
| CZEQ |
TIME RATING PER CHACTERISTIC |
12.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 12.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| CQZP |
INPUT CIRCUIT PATTERN |
QUAD 2 INPUT |
| ADAT |
BODY WIDTH |
0.280 INCHES MAXIMUM |
| CWSG |
TERMINAL SURFACE TREATMENT |
SOLDER |
| CBBL |
FEATURES PROVIDED |
HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND SCHOTTKY AND W/TOTEM POLE OUTPUT |