| CQSZ |
INCLOSURE CONFIGURATION |
DUAL-IN-LINE |
| AFGA |
OPERATING TEMP RANGE |
-55.0/+125.0 DEG CELSIUS |
| CTFT |
CASE OUTLINE SOURCE AND DESIGNATOR |
T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| CSSL |
DESIGN FUNCTION AND QUANTITY |
2 FLIP-FLOP, J-K, MASTER SLAVE |
| TTQY |
TERMINAL TYPE AND QUANTITY |
14 PRINTED CIRCUIT |
| CZEQ |
TIME RATING PER CHACTERISTIC |
50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| ADAU |
BODY HEIGHT |
0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| AFJQ |
STORAGE TEMP RANGE |
-65.0/+150.0 DEG CELSIUS |
| CQSJ |
INCLOSURE MATERIAL |
CERAMIC |
| ADAT |
BODY WIDTH |
0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CQZP |
INPUT CIRCUIT PATTERN |
DUAL 4 INPUT |
| CZEN |
VOLTAGE RATING AND TYPE PER CHARACTERISTIC |
-0.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |
| CBBL |
FEATURES PROVIDED |
POSITIVE OUTPUTS AND W/ENABLE AND HERMETICALLY SEALED AND EDGE TRIGGERED |
| CQWX |
OUTPUT LOGIC FORM |
TRANSISTOR-TRANSISTOR LOGIC |
| TEST |
TEST DATA DOCUMENT |
06481-970086 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| CWSG |
TERMINAL SURFACE TREATMENT |
SOLDER |
| ADAQ |
BODY LENGTH |
0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |